I’ve created a NEORV32 target platform in SweetAda (GitHub - gabriele-galeotti/SweetAda: Ada-language framework).
NEORV32 (GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.) is a RISC-V SoC implementation in VHDL, suited for FPGAs.
The setup is blatantly primitive and runs under simulation by means of GHDL, outputting a welcome message inside the simulated UART console. This setup is still WIP, I have to properly integrate the build
machinery with that of the NEORV32 environment.
So far I have no FPGA hardware (besides the time) ready to create a real implementation, so if someone is using NEORV32 on real hardware, and is willing to test, this will be very interesting. Just a OK/KO flag. The current setup needs only UART clocking parameters in the CTRL register, which I suppose it depends on the actual clock configuration. In the meantime I will try to develop things inside the simulated GHDL environment.
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