I’ve created a NEORV32 target platform in SweetAda (https://github.com/gabriele-galeotti).
NEORV32 (https://github.com/stnolting/neorv32) is a RISC-V SoC implementation in VHDL, suited for FPGAs.
The setup is blatantly primitive and runs under simulation by means of GHDL, outputting a welcome message inside the simulated UART console.
So far I have no FPGA hardware (besides the time) ready to create a real implementation, so if someone is using NEORV32 on real hardware, and is willing to test, that would be very interesting -- just a OK/KO flag.
The current setup needs only UART clocking parameters in the CTRL register, which I suppose it depends on the actual clock configuration. In the meantime I will try to develop things inside the simulated GHDL environment.